View 73K224L-IGT_523987.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

73K224L V.22bis/V.22/V.21/ Bell 212A/Bell 103 Single-Chip Modem
April 2000
DESCRIPTION
The 73K224L is a highly integrated single-chip modem IC which provides the functions needed to construct a V.22bis compatible modem, capable of 2400 bit/s full-duplex operation over dial-up lines. The 73K224L offers excellent performance and a high level of functional integration in a single 28-pin DIP and 44-pin TQFP package. This device supports V.22bis, V.22, V.21, Bell 212A and Bell 103 modes of operation, allowing both synchronous and asynchronous communication. The 73K224L is designed to appear to the systems designer as a microprocessor peripheral, and will easily interface with popular single-chip microprocessors (80C51 typical) for control of modem functions through its 8bit multiplexed address/data bus or via an optional serial control bus. An ALE control line simplifies address demultiplexing. Data communications normally occur through a separate serial port. The 73K224L is pin and software compatible with the 73K212L and 73K222L single-chip modem ICs, allowing system upgrades with a single component change. The 73K224L operates from a single +5V supply for low power consumption. The 73K224L is ideal for use in either free-standing or integral system modem products where full-duplex
(continued)
FEATURES
* * * * * * * * * * * * * *
One-chip multi-mode V.22bis/V.22/V.21 and Bell 212A/103 compatible modem data pump FSK (300 bit/s), DPSK (600, 1200 bit/s), or QAM (2400 bit/s) encoding Pin and software compatible with other TDK Semiconductor Corporation K-Series 1-chip modems Interfaces directly with standard microcontrollers (80C51 typical) Parallel microcontroller bus for modem control and status monitoring functions Selectable asynch/synch with internal buffer/debuffer and scrambler/descrambler functions All synchronous and asynchronous operating modes (internal, external, slave) Adaptive equalization for optimum performance over all lines Programmable transmit attenuation (16 dB, 1 dB steps), selectable receive boost (+18 dB) Call progress, carrier, answer tone, unscrambled mark, S1, and signal quality monitors DTMF, answer and guard tone generators Test modes available: ALB, DL, RDL, Mark, Space, Alternating bit, S1 pattern CMOS technology for low power consumption (typically 100 mW @ 5V) with power-down mode (15 mW @ 5V) TTL and CMOS compatible inputs and outputs
BLOCK DIAGRAM
73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem
DESCRIPTION (continued)
2400 bit/s data communications over the 2-wire switched telephone network is desired. Its high functionality, low power consumption, and efficient packaging simplify design requirements and increase system reliability. The 73K224L is designed to be a complete V.22bis compatible modem on a chip. The complete modem requires only the addition of the phone line interface, a microcontroller for modem control and status monitoring, and RS-232 level converters for a typical system. Many functions were included to simplify implementation of typical modem designs. In addition to the basic 2400 bit/s QAM, 600/1200 bit/s DPSK and 300 bit/s FSK modulator/demodulator sections, the device also includes SYNCH/ASYNCH converters, scrambler/descrambler, call progress tone detect, DTMF tone generator capabilities and handshake pattern detectors. V.22bis, V.22, V.21 and Bell 212A/103 modes are supported (synchronous and asynchronous) and test modes are provided for diagnostics. Most functions are selectable as options and logical defaults are provided. decoded into di-bits and converted back to a serial bit stream. The demodulator also recovers the clock which was encoded into the analog signal during modulation. Demodulation occurs using either a 1200 Hz carrier (answer mode or ALB originate mode) or a 2400 Hz carrier (originate mode or ALB answer mode). Adaptive equalization is also used in DPSK modes for optimum operation with varying line conditions. FSK MODULATOR/DEMODULATOR The FSK modulator produces a frequency modulated analog output signal using two discrete frequencies to represent the binary data. The Bell 103 standard frequencies of 1270 and 1070 Hz (originate mark and space) and 2225 and 2025 Hz (answer mark and space) are used when this mode is selected. V.21 mode uses 980 and 1180 Hz (originate, mark and space) or 1650 and 1850 Hz (answer, mark and space). Demodulation involves detecting the received frequencies and decoding them into the appropriate binary value. The rate converter and scrambler/descrambler are automatically bypassed in the FSK modes. PASSBAND FILTERS AND EQUALIZERS High and low band filters are included to shape the amplitude and phase response of the transmit and receive signals and provide compromise delay equalization and rejection of out-of-band signals. Amplitude and phase equalization are necessary to compensate for distortion of the transmission line and to reduce intersymbol interference in the bandlimited receive signal. The transmit signal filtering corresponds to a 75% square root of raised Cosine frequency response characteristic. ASYNCHRONOUS MODE The Asynchronous mode is used for communication with asynchronous terminals which may communicate at 600,1200, or 2400 bit/s +1%, -2.5% even though the modem's output is limited to the nominal bit rate .01% in DPSK and QAM modes. When transmitting in this mode the serial data on the TXD input is passed through a rate converter which inserts or deletes stop bits in the serial bit stream in order to output a signal that is the nominal bit rate .01%. This signal is then routed to a data scrambler and into the analog modulator where quad-bit/di-bit encoding results in the output signal. Both the rate converter and scrambler can be bypassed for handshaking, and 2
OPERATION
QAM MODULATOR/DEMODULATOR The 73K224L encodes incoming data into quad-bits represented by 16 possible signal points with specific phase and amplitude levels. The baseband signal is then filtered to reduce intersymbol interference on the bandlimited telephone network. The modulator transmits this encoded data using either a 1200 Hz (originate mode) or 2400 Hz (answer mode) carrier. The demodulator, although more complex, essentially reverses this procedure while also recovering the data clock from the incoming signal. Adaptive equalization corrects for varying line conditions by automatically changing filter parameters to compensate for line characteristics. DPSK MODULATOR/DEMODULATOR The 73K224L modulates a serial bit stream into di-bit pairs that are represented by four possible phase shifts as prescribed by the Bell 212A/V.22 standards. The base-band signal is then filtered to reduce intersymbol interference on the bandlimited 2-wire PSTN line. Transmission occurs on either a 1200 Hz (originate mode) or 2400 Hz carrier (answer mode). Demodulation is the reverse of the modulation process, with the incoming analog signal eventually
73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem
synchronous operation as selected. Received data is processed in a similar fashion except that the rate converter now acts to reinsert any deleted stop bits and output data to the terminal at no greater than the bit rate plus 1%. An incoming break signal (low through two characters) will be passed through without incorrectly inserting a stop bit. The SYNC/ASYNC converter also has an extended Overspeed mode which allows selection of an output overspeed range of either +1% or +2.3%. In the extended Overspeed mode, stop bits are output at 7/8 the normal width. Both the SYNC/ASYNC rate converter and the data descrambler are automatically bypassed in the FSK modes. SYNCHRONOUS MODE Synchronous operation is possible only in the QAM or DPSK modes. Operation is similar to that of the Asynchronous mode except that data must be synchronized to a provided clock and no variation in data transfer rate is allowable. Serial input data appearing at TXD must be valid on the rising edge of TXCLK. TXCLK is an internally derived 1200 or 2400 Hz signal in Internal mode and is connected internally to the RXCLK pin in Slave mode. Receive data at the RXD pin is clocked out on the falling edge of RXCLK. The asynch/synch converter is bypassed when Synchronous mode is selected and data is transmitted at the same rate as it is input. PARALLEL BUS INTERFACE Eight 8-bit registers are provided for control, option select, and status monitoring. These registers are addressed with the AD0, AD1, and AD2 multiplexed address lines (latched by ALE) and appear to a control microprocessor as seven consecutive memory locations. Six control registers are read/write memory. The detect and ID registers are read only and cannot be modified except by modem response to monitored parameters. SERIAL CONTROL MODE The serial Command mode allows access to the 73K224 control and status registers via a serial control port. In this mode the AD0, AD1, and AD2 lines provide register addresses for data passed through AD7 (DATA) pin under control of the RD and WR lines. A read operation is initiated when the RD line is taken low. The next eight cycles of EXCLK will then transfer out eight bits of the selected address location LSB first. A write takes place by shifting in eight bits of data LSB first for eight consecutive cycles of EXCLK. WR is then pulsed low and data transfer into the selected register occurs on the rising edge of WR. DTMF GENERATOR The DTMF generator controls the sending of the sixteen standard DTMF tone pairs. The tone pair sent is determined by selecting TRANSMIT DTMF (bit D4) and the 4 DTMF bits (D0-D3) of the TONE register. Transmission of DTMF tones from TXA is gated by the TRANSMIT ENABLE bit of CR0 (bit D1) as with all other analog signals.
3
73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem
PIN DESCRIPTION
POWER NAME GND VDD VREF ISET TYPE I I O I DESCRIPTION System Ground. Power supply input, 5V -5% +10%. Bypass with 0.22 F and 22 F capacitors to GND. An internally generated reference voltage. Bypass with 0.22 F capacitor to GND. Chip current reference. Sets bias current for op-amps. The chip current is set by connecting this pin to VDD through a 2 M resistor. Iset should be bypassed to GND with a 0.22 F capacitor.
PARALLEL MICROPROCESSOR INTERFACE ALE AD0- AD7 CS I I/O
/Tristate
Address latch enable. The falling edge of ALE latches the address on AD0-AD2 and the chip select on CS. Address/data bus. These bidirectional tri-state multiplexed lines carry information to and from the internal registers. Chip select. A low on this pin allows a read cycle or a write cycle to occur. AD0AD7 will not be driven and no registers will be written if CS (latched) is not active. CS is latched on the falling edge of ALE. Output clock. This pin is selectable under processor control to be either the crystal frequency (for use as a processor clock) or 16 x the data rate for use as a baud rate clock in QAM/DPSK modes only. The pin defaults to the crystal frequency on reset. Interrupt. This open drain /weak pull-up, output signal is used to inform the processor that a detect flag has occurred. The processor must then read the detect register to determine which detect triggered the interrupt. INT will stay active until the processor reads the detect register or does a full reset. Read. A low requests a read of the 73K224L internal registers. Data cannot be output unless both RD and the latched CS are active or low. Reset. An active high signal on this pin will put the chip into an inactive state. All control register bits (CR0, CR1, CR2, CR3, Tone) will be reset. The output of the CLK pin will be set to the crystal frequency. An internal pull down resistor permits power on reset using a capacitor to VDD. Write. A low on this informs the 73K224L that data is available on AD0-AD7 for writing into an internal register. Data is latched on the rising edge of WR. No data is written unless both WR and the latched CS are active (low).
I
CLK
O
INT
O
RD RESET
I I
WR
I
NOTE:
The serial control mode is provided by tying ALE high and CS low. In this configuration AD7 becomes DATA and AD0, AD1 and AD2 become the address only.
4
73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem
DTE USER INTERFACE NAME EXCLK TYPE I DESCRIPTION External Clock. This signal is used in synchronous transmission when the external timing option has been selected. In the external timing mode the rising edge of EXCLK is used to strobe synchronous transmit data available on the TXD pin. Also used for serial control interface. Receive Clock. Tri stateable. The falling edge of this clock output is coincident with the transitions in the serial received data output. The rising edge of RXCLK can be used to latch QAM or DPSK valid output data. RXCLK will be active as long as a carrier is present. Received Digital Data Output. Serial receive data is available on this pin. The data is always valid on the rising edge of RXCLK when in synchronous mode. RXD will output constant marks if no carrier is detected. Transmit Clock. Tri stateable. This signal is used in synchronous transmission to latch serial input data on the TXD pin. Data must be provided so that valid data is available on the rising edge of the TXCLK. The transmit clock is derived from different sources depending upon the synchronization mode selection. In Internal Mode the clock is generated internally. In External Mode TXCLK is phase locked to the EXCLK pin. In Slave Mode TXCLK is phase locked to the RXCLK pin. TXCLK is always active. Transmit Digital Data Input. Serial data for transmission is synchronous modes, the data must be valid on the rising clock. In asynchronous modes (2400/1200/600 bit/s or 300 necessary. DPSK data must be +1%, -2.5% or +2.3%, overspeed mode. input on this pin. In edge of the TXCLK baud) no clocking is -2.5 % in extended
RXCLK
O/ Tristate
RXD
O/ Weak Pull-up O/ Tristate
TXCLK
TXD
I
ANALOG INTERFACE AND OSCILLATOR RXA TXA XTL1 XTL2 I O I I/O Received modulated analog signal input from the phone line. Transmit analog output to the phone line. These pins are for the internal crystal oscillator requiring a 11.0592 MHz parallel mode crystal. Two capacitors from these pins to ground are also required for proper crystal operation. Consult crystal manufacturer for proper values. XTL2 can also be driven from an external clock.
5
73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem
REGISTER DESCRIPTIONS
Eight 8-bit internal registers are accessible for control and status monitoring. The registers are accessed in read or write operations by addressing the A0, A1 and A2 address lines in serial mode, or the AD0, AD1 and AD2 lines in parallel mode. The address lines are latched by ALE. Register CR0 controls the method by which data is transferred over the phone line. CR1 controls the interface between the microprocessor and the 73K224L internal state. DR is a detect register REGISTER BIT SUMMARY which provides an indication of monitored modem status conditions. TR, the tone control register, controls the DTMF generator, answer and guard tones and RXD output gate used in the modem initial connect sequence. CR2 is the primary DSP control interface and CR3 controls transmit attenuation and receive gain adjustments. All registers are read/write except for DR and ID which are read only. Register control and status bits are identified below:
6
73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem
REGISTER ADDRESS TABLE
ADDRESS REGISTER AD2 - AD0 D7 D6 D5 DATA BIT NUMBER D4 D3 D2 D1 D0
CONTROL REGISTER 0
CR0
000
MODULATION OPTION
MODULATION TYPE 1
MODULATION TYPE 0
TRANSMIT MODE 2
TRANSMIT MODE 1
TRANSMIT MODE 0
TRANSMIT ENABLE
ANSWER/ ORIGINATE
QAM: 0=2400 BIT/S DPSK: 0=1200 BIT/S 1=600 BIT/S FSK: 0=103 MODE 1=V.21
10=QAM 00=DPSK 01=FSK
0000=PWR DOWN 0001=INT SYNCH 0010=EXT SYNCH 0011=SLAVE SYNCH 0100=ASYCH 8 BITS/CHAR 0101=ASYCH 9 BITS/CHAR 0110=ASYCH 10 BITS/CHAR 0111=ASYCH 11 BITS/CHAR 1X00=FSK ENABLE DETECT INTERRUPT BYPASS SCRAMBLER CLK CONTROL
0=DISABLE TXA OUTPUT 1=ENABLE TXA OUTPUT
0=ANSWER 1=ORIGINATE
CONTROL REGISTER 1
CR1
001
TRANSMIT PATTERN 1
TRANSMIT PATTERN 0
RESET
TEST MODE 1
TEST MODE 0
00=TX DATA 01=TX ALTERNATE 10=TX MARK 11=TX SPACE
0=DISABLE 1=ENABLE
0=NORMAL 1=BYPASS SCRAMBLER
0=XTAL 1=16 X DATA RATE OUTPUT AT CLK PIN IN QAM/DPSK MODE ONLY CARRIER DETECT
0=NORMAL 1=RESET
00=NORMAL 01=ANALOG LOOPBACK 10=REMOTE DIGITAL LOOPBACK 11=LOCAL DIGITAL LOOPBACK CP TONE DETECT SIGNAL QUALITY INDICATOR 0=GOOD 1=BAD
DETECT REGISTER
DR
010
RECEIVE LEVEL INDICATOR 0=SIGNAL BELOW THRESHOLD 1=ABOVE THRESHOLD
S1 PATTERN DETECT
RECEIVE DATA
UNSCR. MARKS DETECT
ANSWER TONE DETECT
0=NOT PRESENT 1=PATTERN FOUND
OUTPUTS RECEIVED DATA STREAM
0=CONDITION NOT DETECTED 1=CONDITION DETECTED
TONE CONTROL REGISTER
TR
011
RXD OUTPUT CONTROL RXD PIN 0=NORMAL 1=OPEN
TRANSMIT GUARD TONE
TRANSMIT ANSWER TONE 0=OFF 1=ON
TRANSMIT DTMF
DTMF3
DTMF2/ 4 W/FDX
DTMF1/ EXTENDED OVERSPEED
DTMF0/ GUARD/ ANSWER/ CALLING/SCT
0=OFF 1=ON
0=DATA 1=TX DTMF
4 BIT CODE FOR 1 OF 16 DUAL TONE COMBINATIONS
0=1800 Hz G.T. 2225 Hz ANS TONE GENERATED 1= 550 Hz G.T. 2100 Hz ANS TONE GENERATED & DETECTED (V.21, V.22)
CONTROL REGISTER 2
CR2
100
0
SPECIAL REGISTER ACCESS 0=ACCESS CR3 1=ACCESS SPECIAL REGISTER
CALL INITIALIZE
TRANSMIT S1
16 WAY
RESET DSP
TRAIN INHIBIT
EQUALIZER ENABLE
0=DSP IN 0=NORMAL DEMOD MODE DOTTING 1=DSP IN CALL 1=S1 PROGRESS MODE
0=RX=TX 1=RX=16 WAY
0=DSP INACTIVE 1=DSP ACTIVE
0=ADAPT EQ ACTIVE 1=ADAPT EQ FROZEN
0=ADAPT EQ IN INIT 1=ADAPT EQ OK TO ADAPT
CONTROL REGISTER 3
CR3
101
TXDALT ALTERNATE TRANSMIT DATA SOURCE
TRISTATE TX/RXCLK 0=NORMAL 1=TRISTATE
0
RECEIVE GAIN BOOST 0=NO BOOST 1=18 dB BOOST
TRANSMIT ATTEN. 3
TRANSMIT ATTEN. 2
TRANSMIT ATTEN. 1
TRANSMIT ATTEN. 0
0000-1111, SETS TRANSMIT ATTENUATOR 16 dB RANGE DEFAULT=0100 -10 dbM0 TXD SOURCE SQ SELECT1 SQ SELECT0
SPECIAL REGISTER
SR
101
0
TX BAUD CLOCK
RX UNSCR. DATA
0
0
OUTPUTS TXBAUD CLOCK
OUTPUTS UNSCR. DATA
0=TXD PIN 1=TXALT BIT
-5 0010 BER -6 0110 BER -4 1010 BER -3 1110 BER
ID REGISTER
10
110
ID
ID
ID
ID
X
X
X
X
00XX=73K212AL, 322L, 321L 01XX=73K221AL, 302L 10XX=73K222AL, 222BL 1100=73K224L 1110=73K324L 1100=73K224BL 1110=73K324BL
7
73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem
CONTROL REGISTER 0
D7 CR0 000 MODUL. OPTION D6 MODUL. TYPE 1 D5 MODUL. TYPE 0 D4 TRANSMIT MODE 2 D3 TRANSMIT MODE 1 D2 TRANSMIT MODE 0 D1 TRANSMIT ENABLE D0 ANSWER/ ORIGINATE
BIT NO. D0
NAME Answer/ Originate
CONDITION 0 1
DESCRIPTION Selects answer mode (transmit in high band, receive in low band). Selects originate mode (transmit in low band, receive in high band). Disables transmit output at TXA. Enables transmit output at TXA. Note: Transmit Enable must be set to 1 to allow activation of Answer Tone or DTMF.
D1
Transmit Enable
0 1
D5 D4 0 0 D5, D4, D3, D2 Transmit Mode 0 0
D3 D2 0 0 0 1 Selects power down mode. All functions disabled except digital interface. Internal synchronous mode. In this mode TXCLK is an internally derived 600,1200 or 2400 Hz signal. Serial input data appearing at TXD must be valid on the rising edge of TXCLK. Receive data is clocked out of RXD on the falling edge of RXCLK. External synchronous mode. Operation is identical to internal synchronous, but TXCLK is connected internally to EXCLK pin, and a 600, 1200 or 2400 Hz clock must be supplied externally. Slave synchronous mode. Same operation as other synchronous modes. TXCLK is connected internally to the RXCLK pin in this mode. Selects asynchronous mode - 8 bits/character (1 start bit, 6 data bits, 1 stop bit). Selects asynchronous mode - 9 bits/character (1 start bit, 7 data bits, 1 stop bit). Selects asynchronous mode - 10 bits/character (1 start bit, 8 data bits, 1 stop bit). Selects asynchronous mode - 11 bits/character (1 start bit, 8 data bits, Parity and/or 1 or 2 stop bits). Selects FSK operation. QAM DPSK FSK
0
0
1
0
0
0
1
1
0 0 0 0 1 D6,D5 Modulation Type
1 1 1 1 X D6 1 0 0
0 0 1 1 0 D5 0 0 1
0 1 0 1 0
8
73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem
CONTROL REGISTER 0 (continued)
D7 CR0 000 MODUL. OPTION D6 MODUL. TYPE 1 D5 MODUL. TYPE 0 D4 TRANSMIT MODE 2 D3 TRANSMIT MODE 1 D2 TRANSMIT MODE 0 D1 TRANSMIT ENABLE D0 ANSWER/ ORIGINATE
BIT NO. D7
NAME Modulation Option
CONDITION 0 1
DESCRIPTION QAM selects 2400 bit/s. DPSK selects 1200 bit/s. FSK selects 103 mode. DPSK selects 600 bit/s. FSK selects V.21 mode.
CONTROL REGISTER 1
D7 CR1 001 TRANSMIT PATTERN 1 D6 TRANSMIT PATTERN 0 D5 ENABLE DETECT INT. D4 BYPASS SCRAMB D3 CLK CONTROL D2 RESET D1 TEST MODE 1 D0 TEST MODE 0
BIT NO. D1, D0
NAME Test Mode
CONDITION D1 0 0 D0 0 1
DESCRIPTION Selects normal operating mode. Analog loopback mode. Loops the transmitted analog signal back to the receiver, and causes the receiver to use the same carrier frequency as the transmitter. To squelch the TXA pin, TRANSMIT ENABLE bit as well as Tone Reg bit D2 must be low. Selects remote digital loopback. Received data is looped back to transmit data internally, and RXD is forced to a mark. Data on TXD is ignored. Selects local digital loopback. Internally loops TXD back to RXD and continues to transmit data carrier at TXA pin. Selects normal operation. Resets modem to power down state. All control register bits (CR0, CR1, CR2, CR3 and Tone) are reset to zero except CR3 bit D2. The output of the clock pin will be set to the crystal frequency. Selects 11.0592 MHz crystal echo output at CLK pin. Selects 16 X the data rate, output at CLK pin in DPSK/QAM modes only.
1
0
1 D2 Reset 0 1
1
D3
Clock Control
0 1
9
73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem
CONTROL REGISTER 1 (continued)
D7 CR1 001 TRANSMIT PATTERN 1 D6 TRANSMIT PATTERN 0 D5 ENABLE DETECT INT. D4 BYPASS SCRAMB D3 CLK CONTROL D2 RESET D1 TEST MODE 1 D0 TEST MODE 0
BIT NO. D4
NAME Bypass Scrambler
CONDITION 0 1
DESCRIPTION Selects normal operation. DPSK and QAM data is passed through scrambler. Selects Scrambler Bypass. Bypass DPSK and QAM data is routed around scrambler in the transmit path. Disables interrupt at INT pin. All interrupts are normally disabled in power down mode. Enables INT output. An interrupt will be generated with a change in status of DR bits D1-D4 and D6. The answer tone and call progress detect interrupts are masked when the TX enable bit is set. Carrier detect is masked when TX DTMF is activated. All interrupts will be disabled if the device is in power down mode.
D5
Enable Detect Interrupt
0 1
D7 D7, D6 Transmit Pattern 0 0
D6 0 1 Selects normal data transmission as controlled by the state of the TXD pin. Selects an alternating mark/space transmit pattern for modem testing and handshaking. Also used for S1 pattern generation. See CR2 bit D4. Selects a constant mark transmit pattern. Selects a constant space transmit pattern.
1 1 DETECT REGISTER
D7 DR 010 RECEIVE LEVEL INDICATOR D6 S1 PATTERN DETECT
0 1
D5 RECEIVE DATA
D4 UNSCR MARK. DETECT
D3 CARR. DETECT
D2 ANSWER TONE DETECT
D1 CALL PROG. DETECT
D0 SIGNAL QUALITY INDICATOR
BIT NO. D0
NAME Signal Quality Indicator Call Progress Detect
CONDITION 0 1 0 1
DESCRIPTION Indicates normal received signal. Indicates low received signal quality (above average error rate). Interacts with special register bits D2, D1. No call progress tone detected. Indicates presence of call progress tones. The call progress detection circuitry is activated by energy in the normal 350 to 620 Hz call progress bandwidth.
D1
10
73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem
DETECT REGISTER (continued)
D7 DR 010 RECEIVE LEVEL INDICATOR D6 S1 PATTERN DETECT D5 RECEIVE DATA D4 UNSCR. MARK DETECT D3 CARR. DETECT D2 ANSWER TONE DETECT D1 CALL PROG. D0 SIGNAL QUALITY INDICATOR
BIT NO. D2
NAME Answer Tone Received
CONDITION 0 1
DESCRIPTION No answer tone detected. In Call Init mode, indicates detection of 2225 Hz answer tone in Bell mode (TR bit D0=0) or 2100 Hz if in CCITT mode (TR bit D0=1). The device must be in originate mode for detection of answer tone. Both answer tones are detected in demod mode. No carrier detected in the receive channel. Indicated carrier has been detected in the received channel. No unscrambled mark. Indicates detection of unscrambled marks in the received data. Should be time qualified by software. Continuously outputs the received data stream. This data is the same as that output on the RXD pin, but it is not disabled when RXD is tri-stated.
D3
Carrier Detect
0 1
D4
Unscrambled Mark Detect Receive Data
0 1
D5
D6
S1 Pattern Detect
0 1
No S1 pattern being received. S1 pattern detected. Should be time qualified by software. S1 pattern is defined as a double di-bit (001100..) unscrambled 1200 bit/s DPSK signal. Pattern must be aligned with baud clock to be detected. Received signal level below threshold, (typical -25 dBm0); can use receive gain boost (+18 dB). Received signal above threshold.
D7
Receive Level Indicator
0 1
TONE REGISTER
D7 TR 011 RXD OUTPUT CONTR. D6 TRANSMIT GUARD TONE D5 TRANSMIT ANSWER TONE D4 TRANSMIT DTMF D3 DTMF 3 D2 DTMF 2 D1 DTMF 1/ EXTENDED OVER- SPEED D0 DTMF 0/ ANSWER/ GUARD
BIT NO. D0
NAME DTMF 0/ Answer/ Guard Tone
CONDITION D6 D5 X X X X 1 1 D4 D0 1 0 0 X 0 1
DESCRIPTION D0 interacts with bits D6, D5, and D4 as shown. Transmit DTMF tones. Select Bell mode answer tone. Interacts with DR bit D2 and TR bit D5. Select CCITT mode answer tone. Interacts with DR bit D2 and TR bit D5.
11
73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem
TONE REGISTER (continued)
D7 TR 011 RXD OUTPUT CONTR. D6 TRANSMIT GUARD TONE D5 TRANSMIT ANSWER TONE D4 TRANSMIT DTMF D3 DTMF 3 D2 DTMF 2/4 WIRE FDX D1 DTMF 1/ EXTENDED OVER- SPEED D0 DTMF 0/ ANSWER/ GUARD
BIT NO. D0
NAME DTMF 0/ Answer/ Guard Tone DTMF 1/ Extended Overspeed 1 1
CONDITION D6 D5 0 0 D4 0 0 D4 D4 D0 0 0 D1 0 1 D2 0 1 0 1
DESCRIPTION D0 interacts with bits D6, D5, and D4 as shown. Select 1800 Hz guard tone. Select 550 Hz guard tone. D1 interacts with D4 as shown. Asynchronous QAM or DPSK +1.0% -2.5%. (normal) Asynchronous QAM or DPSK +2.3% -2.5%. (extended overspeed) Selects 2 wire duplex or half duplex D2 selects 4 wire full duplex in the modulation mode selected. The receive path corresponds to the ANS/ORIG bit CR0 D0 in terms of high or low band selection. The transmitter is in the same band as the receiver, but does not have magnitude filtering or equalization on its signal as in the receive path.
D1
D2
DTMF 2/4 WIRE FDX
0 0
12
73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem
TONE REGISTER (continued)
D7 TR 011 RXD OUTPUT CONTR. D6 TRANSMIT GUARD TONE D5 TRANSMIT ANSWER TONE D4 TRANSMIT DTMF D3 DTMF 3 D2 DTMF 2/4 WIRE FDX D1 DTMF 1/ EXTENDED OVER- SPEED D0 DTMF 0/ ANSWER GUARD
BIT NO. D3, D2, D1, D0
NAME DTMF 3, 2, 1, 0
CONDITION D4 = 1
DESCRIPTION Programs 1 of 16 DTMF tone pairs that will be transmitted when TX DTMF and TX enable bit (CR0, bit D1) is set. Tone encoding is shown below: KEYBOARD EQUIVALENT 1 2 3 4 5 6 7 8 9 0 * # A B C D DTMF CODE D3 D2 D1 D0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 TONES LOW HIGH 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 1633
D4
TX DTMF (Transmit DTMF)
0 1
Disable DTMF. Activate DTMF. The selected DTMF tones are transmitted continuously when this bit is high. TX DTMF overrides all other transmit functions.
Note: DTMF0 - DTMF2 should be set to an appropriate state after DTMF dialing to avoid unintended operation.
13
73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem
TONE REGISTER (continued)
D7 TR 011 RXD OUTPUT CONTR. D6 TRANSMIT GUARD TONE D5 TRANSMIT ANSWER TONE D4 TRANSMIT DTMF D3 DTMF 3 D2 DTMF 2/4 WIRE FDX D1 DTMF 1/ EXTENDED OVER- SPEED D0 DTMF 0/ ANSWER/ GUARD
BIT NO. D5
NAME Transmit Answer Tone
CONDITION D5 D4 D0
DESCRIPTION D5 interacts with bits D4 and D0 as shown. Also interacts with DR bit D2 in originate mode. See Detect Register description. Disables answer tone generator. In answer mode, a Bell 2225 Hz tone is transmitted continuously when the Transmit Enable bit is set. Likewise, a CCITT 2100 Hz answer tone is transmitted. Disables guard tone generator. Enables guard tone generator. (See D0 for selection of guard tones.) Bit D4 must be zero. Enables RXD pin. Receive data will be output on RXD. Disables RXD pin. The RXD pin reverts to a high impedance with internal weak pull-up resistor.
0 1 1 D6 Transmit Guard Tone RXD Output Control
0 0 0 0 1 0 1
X 0 1
D7
CONTROL REGISTER 2
D7 CR2 100 0 D6 SPEC REG ACCESS D5 CALL INIT D4 TRANSMIT S1 D3 16 WAY D2 RESET DSP D1 TRAIN INHIBIT D0 EQUALIZER ENABLE
BIT NO. D0
NAME Equalizer Enable
CONDITION 0 1
DESCRIPTION The adaptive equalizer is in its initialized state. The adaptive equalizer is enabled. This bit is used in handshakes to control when the equalizer should calculate its coefficients. The adaptive equalizer is active. The adaptive equalizer coefficients are frozen. The DSP is inactive and all variables are initialized. The DSP is running based on the mode set by other control bits The receiver and transmitter are using the same decision plane (based on the Modulator Control Mode). The receiver, independent of the transmitter, is forced into a 16 point decision plane. Used for QAM handshaking.
D1 D2
Train Inhibit RESET DSP
0 1 0 1
D3
16 Way
0 1
14
73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem
CONTROL REGISTER 2 (continued)
D7 CR2 100 0 D6 SPEC REG ACCESS D5 CALL INIT D4 TRANSMIT S1 D3 16WAY D2 RESET DSP D1 TRAIN INHIBIT D0 EQUALIZER ENABLE
BIT NO. D4
NAME Transmit S1
CONDITION 0
1
D5
Call Init
0
1 D6 Special Register Access
Not used at this time
0 1
D7
0
DESCRIPTION The transmitter when placed in alternating mark/space mode transmits 0101...... scrambled or not dependent on the bypass scrambler bit. When this bit is 1 and only when the transmitter is placed in alternating mark/space mode by CR1 bits D7, D6, and in DPSK or QAM, an unscrambled repetitive double dibit pattern of 00 and 11 at 1200 bit/s (S1) is sent. DEMOD mode: The DSP is setup to do demodulation and pattern detection based on the various mode bits. Both answer tones are detected in demod mode concurrently (wide band detection); TR-D0 is ignored. CALL INIT mode: The DSP decodes unscrambled mark, answer tone and call progress tones. Normal CR3 access. Setting this bit and addressing CR3 allows access to the SPECIAL REGISTER. See the SPECIAL REGISTER for details. Only write zero to this bit.
CONTROL REGISTER 3
CR3 101 D7 TXDALT D6 TRISTATE TX/RXCLK D5 0 D4 RECEIVE BOOST ENABLE D3 TRANSMIT ATTEN. 3 D2 TRANSMIT ATTEN. 2 D1 TRANSMIT ATTEN. 1 D0 TRANSMIT ATTEN. 0
BIT NO. D3, D2, D1,D0
NAME Transmit Attenuator
CONDITION D3 D2 0 0 1 1 0 1 D1 D0 0 0 1 1
DESCRIPTION Sets the attenuation level of the transmitted signal in 1dB steps. The default (D3-D0=0100) is for a transmit level of - 10 dBm0 on the line with the recommended hybrid transmit gain. The total range is 16 dB. 18 dB receive front end boost is not used. Boost is in the path. This boost does not change reference levels. It is used to extend dynamic range by compensating for internally generated noise when receiving weak signals. The receive level detect signal and knowledge of the hybrid and transmit attenuator setting will determine when boost should be enabled. Only write zero to this bit. TXCLK and RXCLK are driven. TXCLK and RXCLK are tri-stated. Alternate TX data source. See Special Register.
D4
Receive Gain Boost
Not used at this time
D5 D6 D7
TRISTATE TXCLK/RXCLK TXDALT
0 0 1
Spec. Reg. Bit D3=1
15
73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem
SPECIAL REGISTER
D7 SR 101 0 D6 TXBAUD CLOCK D5 RXUNDSCR DATA D4 0 D3 TXD SOURCE D2 SIGNAL QUALITY LEVEL SELECT1 D1 SIGNAL QUALITY LEVEL SELECT0 D0 0
BIT NO. D7, D4, D0 D6
NAME TXBAUD CLK
DESCRIPTION NOT USED AT THIS TIME. Only write ZEROs to these bits. TXBAUD clock is the transmit baud-synchronous clock that can be used to synchronize the input of arbitrary quad/di-bit patterns. The rising edge of TXBAUD signals the latching of a baud-worth of data internally. Synchronous data to be entered via the TXDALT bit, CR3 bit D7, should have data transitions that start 1/2 bit period delayed from the TXBAUD clock edges. This bit outputs the data received before going to the descrambler. This is useful for sending special unscrambled patterns that can be used for signaling. This bit selects the transmit data source; either the TXD pin if ZERO or the TXDALT if this bit is a ONE. The TRANSMIT PATTERN bits D7 and D6 in CR1 override either of these sources. The signal quality indicator is a logical ZERO when the signal received is acceptable for low error rate reception. It is determined by the value of the Mean Squared Error (MSE) calculated in the decisioning process when compared to a given threshold. This threshold can be set to four levels of error rate. The SQI bit will be low for good or average connections. As the error rate crosses the threshold setting, the SQI bit will toggle at a 1.66 ms rate. Toggling will continue until the error rate indicates that the data pump has lost convergence and a retrain is required. At that point the SQI bit will be a ONE constantly. The SQI bit and threshold selection are valid for QAM and DPSK only and indicates typical error rate. THRESHOLD VALUE 10-5 10-6 10-4 10
-3
D5
RXUNDSCR DATA TXD SOURCE
D3
D2, D1
SIGNAL QUALITY LEVEL SELECT
D2 0 0 1 1
D1 0 1 0 1
UNITS BER (default) BER BER BER
NOTE: This register is "mapped" and is accessed by setting CR2 bit D6 to a ONE and addressing CR3. This register provides functions to the 73K224L user that are not necessary in normal communications. Bits D7-D4 are read only, while D3-D0 are read/write. To return to normal CR3 access, CR2 bit D6 must be returned to a ZERO.
16
73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem
ID REGISTER D7 ID 110 BIT NO. D7, D6, D5, D4 ID 3 D6 ID 2 NAME Device Identification Signature 0 0 1 1 1 1 1 D3-D1 D0 Not Used Version D5 ID 1 CONDITION D7 D6 0 1 0 1 1 1 1 1 D5 D4 X X X 0 1 0 1 X X X 0 0 0 0 D4 ID 0 D3 X DESCRIPTION Indicates Device: 73K212AL, 73K321L or 73K322L 73K221AL or 73K302L 73K222AL, 73K222BL 73K224L 73K324L 73K224BL 73K324BL Mask in software Indicates industrial temperature version D2 X D1 X D0 1
Undefined
17
73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS PARAMETER VDD Supply Voltage Storage Temperature Soldering Temperature (10 sec.) Applied Voltage RATING 7V -65 to 150C 260C -0.3 to VDD+0.3V
Note: All inputs and outputs are protected from static charge using built-in, industry standard protection devices and all outputs are short-circuit protected. RECOMMENDED OPERATING CONDITIONS PARAMETER VDD Supply voltage External Components (Refer to Application section for placement.) VREF Bypass capacitor Bias setting resistor ISET Bypass capacitor VDD Bypass capacitor 1 VDD Bypass capacitor 2 XTL1 Load Capacitance XTL2 Load Capacitance Clock Variation TA, Operating Free-Air Temperature (VREF to GND)
(Placed between VDD and ISET pins)
CONDITION
MIN 4.5 0.22 1.8 0.22 0.22 22
NOM 5
MAX 5.5
UNIT V F
2
2.2
M F F F
(ISET pin to GND) (VDD to GND) (VDD to GND) Depends on crystal requirements Depends on crystal requirements
(11.0592 MHz) Crystal or external clock
18 18 -0.01 -40
39 27 +0.01 85
pF pF % C
18
73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem
DC ELECTRICAL CHARACTERISTICS (TA = -40C to 85C, VDD = recommended range unless otherwise noted.) PARAMETER IDD, Supply Current IDD1, Active IDD2, Idle Digital Inputs VIL, Input Low Voltage VIH, Input High Voltage All Inputs except Reset XTL1, XTL2 Reset, XTL1, XTL2 IIH, Input High Current IIL, Input Low Current Reset Pull-down Current Digital Outputs VOH, Output High Voltage VOL, Output Low Voltage RXD Tri-State Pull-up Curr. Capacitance CLK Input Capacitance Maximum permitted load All digital inputs 25 10 pF pF IO = IOH Min IOUT = -0.4 mA IO = IOUT = 1.6 mA RXD = GND -2 2.4 VDD 0.4 -50 V V A VI = VDD VI = 0V Reset = VDD -200 2 50 2.0 3.0 VDD VDD 100 V V A A A 0.8 V CONDITION CLK = 11.0592 MHz ISET Resistor = 2 M Operating with crystal oscillator, < 5 pF capacitive load on CLK pin 18 3 25 5 mA mA MIN NOM MAX UNIT
19
73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem
ELECTRICAL SPECIFICATIONS (continued)
DYNAMIC CHARACTERISTICS AND TIMING (TA = -40C to +85C, VDD = recommended range unless otherwise noted.) PARAMETER QAM/DPSK Modulator Carrier Suppression Output Amplitude FSK Modulator/Demodulator Output Freq. Error Transmit Level TXA Output Distortion Output Bias Distortion at RXD Output Jitter at RXD Sum of Bias Distortion and Output Jitter Output Amplitude Output Distortion DTMF Generator Freq. Accuracy Output Amplitude Output Amplitude Twist Receiver Dynamic Range Call Progress Detector Detect Level Reject Level Delay Time Hold Time -70 dBm0 to -30 dBm0 STEP -30 dBm0 to -70 dBm0 STEP
Low Band, ATT = 0100, DPSK Mode High Band, ATT = 0100, DPSK Mode High-Band to Low-Band, DPSK Mode
CONDITION Measured at TXA TX scrambled marks ATT = 0100 (default) CLK = 11.0592 MHz ATT = 0100 (Default) Transmit Dotting Pattern All products through BPF Dotting Pattern measured at RXD Receive Level -20 dBm, SNR 20 dB Integrated for 5 seconds Integrated for 5 seconds
MIN 35 -11.5
NOM
MAX
UNIT dB
-10.0
-9
dBm0
-0.31 -11.5 -10.0
+0.20 -9 -45
% dBm0 dB % % %
-10 -15 -17
+10 +15 +17
Answer Tone Generator (2100 or 2225 Hz) ATT = 0100 (Default Level) Not in V.21 Distortion products in receive band Not in V.21 -0.03 -10 -8 1.0 -43 -34 2.0 +0.25 -8 -6 3.0 -3.0 0 -40 25 25 % dBm0 dBm0 dB dBm0 dBm0 dBm0 ms ms -11.5 -10 -9 -40 dBm0 dB
Refer to Performance Curves In Call Init mode 460 Hz test signal
NOTE: Parameters expressed in dBm0 refer to the following definition: 0 dB loss in the Transmit path from TXA to the line. 2 dB gain in the Receive path from the line to RXA. Refer to the Basic Box Modem diagram in the Applications section for the DAA design.
20
73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (continued) PARAMETER Carrier Detect Threshold Hysteresis Delay Time FSK DPSK QAM Hold Time FSK DPSK QAM Answer Tone Detectors Detect Level Detect Time Hold Time Pattern Detectors S1 Pattern Delay Time Hold Time Unscrambled Mark Delay Time Hold Time Receive Level Indicator Detect On Valid after Carrier Detect Output Smoothing Filter Output Impedance Output load TXA pin TXA pin; FSK Single Tone out for THD = -50 dB in 0.3 to 3.4 kHz range Maximum Transmitted Energy 4 kHz, Guard Tones off 10 kHz, Guard Tones off 12 kHz, Guard Tones off 10 50 -35 -55 -65 200 300 K pF dBm0 dBm0 dBm0 DPSK Mode -22 1 4 -28 7 dBm0 ms For signals from -6 to -40 call Init Mode 10 10 45 45 ms ms For signals from -6 to -40 dBm0, -6 to -40 dBm0, Demod Mode 10 10 55 45 ms ms DPSK Mode Call Init Mode, 2100 or 2225 Hz CONDITION All Modes All Modes 70 dBm0 to -6 dBm0 70 dBm0 to -40 dBm0 -70 dBm0 to -6 dBm0 -70 dBm0 to -40 dBm0 -70 dBm0 to -6 dBm0 -70 dBm0 to -40 dBm0 -6 dBm0 to -70 dBm0 -40 dBm0 to -70 dBm0 -6 dBm0 to -70 dBm0 -40 dBm0 to -70 dBm0 -6 dBm0 to -70 dBm0 -40 dBm0 to -70 dBm0 DPSK Mode -48 6 6 -43 50 50 dBm0 ms ms 25 25 7 7 25 25 25 15 20 14 25 18 MIN -48 2 37 37 17 17 37 37 37 30 29 21 32 28 ms ms ms ms ms ms ms ms ms ms ms ms NOM MAX -43 UNIT dBm0
Receive Gain = On for lower input level measurements
21
73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (continued) PARAMETER Anti Alias Low Pass Filter Out of Band Signal Energy (Defines Hybrid Trans- Hybrid loss requirements) Level at RXA pin with receive Boost Enabled Scrambled data at 2400 bit/s in opposite band Sinusoids out of band Transmit Attenuator Range of Transmit Level Step Accuracy Output Impedance Clock Noise TXA pin; 153.6 kHz Carrier Offset Capture Range Recovered Clock Capture Range Guard Tone Generator Tone Accuracy Tone Level (Below QAM/DPSK Output) Harmonic Distortion (700 to 2900 Hz) 550 Hz 1800 Hz 550 Hz 1800 Hz 550 Hz 1800 Hz -4.5 -7.5 +1.2 -0.8 -3.0 -6.1 -1.5 -4.5 -50 -50 dB dB dB dB % % of frequency (originate or answer) -0.02 +0.02 % Originate or Answer 5 Hz 1.5 mVrms
Default ATT=0100 (-10 dBm0) 1111-0000
CONDITION
MIN
NOM
MAX
UNIT
-14 -9 -21 -0.15 200 -6 +0.15 300
dBm dBm dBm0 dB
22
73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (continued) Timing (Refer to Timing Diagrams) PARAMETER Parallel Mode TAL TLA TLC TCL TRD TLL TRDF TRW TWW TDW TWD Serial Mode TRCK TAR TRA TRD TRDF TCKDR TWW TAW TWA TCKDW TCKW TDCK T1, T2 Clock High after RD Low Address setup before RD Low Address hold after RD Low RD to Data valid Data float after RD High Read Data out after Falling Edge of EXCLK WR width Address setup before WR Low Address hold after Rising Edge of WR Write Data hold after Falling Edge of EXCLK WR High after Falling Edge of EXCLK Data setup before Falling Edge of EXCLK Minimum Period 350 50 50 200 330 50 500 T1 + T2 250 0 350 300 40 300 T1 ns ns ns ns ns ns ns ns ns ns ns ns ns CS/Addr. setup before ALE Low CS/Addr. hold after ALE Low ALE Low to RD/WR Low RD/ WR Control to ALE High Data out from RD Low ALE width Data float after RD High RD width WR width Data setup before WR High Data hold after WR High 70 70 70 20 25 40 30 6 40 10 90 ns ns ns ns ns ns ns ns ns ns ns CONDITION MIN NOM MAX UNIT
NOTE: T1 and T2 are the low/high periods, respectively, of EXCLK in serial mode. NOTE: Asserting ALE, CS, and RD or WR concurrently can cause unintentional register accesses. When using non-8031 compatible processors, care must be taken to prevent this from occurring when designing the interface logic.
23
73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem
TIMING DIAGRAMS
BUS TIMING DIAGRAM (PARALLEL CONTROL MODE )
TLL ALE TLC RD WR TLA TAL AD0-AD7 CS ADDRESS READ DATA ADDRESS TRD TRDF TDW WRITE DATA TWD TRW TCL TLC TWW
READ TIMING DIAGRAM (SERIAL CONTROL MODE )
T1 EXCLK T2
TRCLK RD TAR TRA A0-A2 ADDRESS
TRD DATA D0 D1
TCKDR D2 D3 D4 D5 D6 D7
TRDF
WRITE TIMING DIAGRAM (SERIAL CONTROL MODE)
T2 EXCLK T1 WR TCKW TAW TWA A0-A2 ADDRESS
TWW
TDCK DATA D0 D1 D2 D3 D4 D5 D6 D7
TCKDW
24
73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem
APPLICATIONS INFORMATION
GENERAL CONSIDERATIONS Figures 1 and 2 show basic circuit diagrams for K-Series modem integrated circuits. K-Series products are designed to be used in conjunction with a control processor, a UART or RS-232 serial data interface, and a DAA phone line interface to function as a typical intelligent modem. The K-Series ICs interface directly with Intel 8048 and 80C51 microprocessors for control and status monitoring purposes. Two typical DAA arrangements are shown: one for a split 5 or 12V design and one for a single 5V design. These diagrams are for reference only and do not represent production-ready modem designs. K-Series devices are available with two control interface versions: one for a parallel multiplexed address/data interface, and one for a serial interface. The parallel version is intended for use with 8039/48 or 8031/51 microcontrollers from Intel or many other manufacturers. The serial interface can be used with other microcontrollers or in applications where only a limited number of port lines are available or the application does not lend itself to a multiplexed address/data interface. The parallel versions may also be used in the serial mode, as explained in the data sheet pin description. In most applications the controller will monitor the serial data for commands from the DTE and the received data for break signals from the far end modem. In this way, commands to the modem are sent over the same line as the transmitted data. In other applications the RS-232 interface handshake lines are used for modem control.
+
C8 22 F
C14 39 pF Y1 11.0592 MHZ N/C
C13 18 pF +5V
R10 2.2M XTL1 INT CLK INT XTL1 XTL2 VDD ISET GND RD WR ALE CS RXA K-SERIES LOW POWER FAMILY TXA C7 0.1 F RESET TXA +5V C12 1 F R6 20K C6 0.1 F RXA VREF C10 0.1 F C11 0.1 F C9 0.1 F
RS232 LEVEL CONVERTERS CA CB CC CD CF RTS CTS DSR DTR DCD
XTL2 80C51 P1.0 P1.1 P1.2 P1.3 P1.5 P1.6
C1 390 pF
P0.0-7 RD WR ALE P3.1 P3.2
R5 37.4K R4 20K LM 1458 U1A C2 300 pF R7 43.2K C3 1000 pF
R4 5.1K R3 3.6K
+
P3.0 P1.7 RESET BA BB DA DD DB U5, U6 MC145406 TXD RXD EXCLK RXCLK TXCLK
V+ LM 1458
-
R1 U1B V- 475 1% D3, D4 4.7V ZENER C4 0.033 F
T1 MIDCOM 671-8005 C5 0.47 F 250V U2 4N35 D1 IN4004 +5V K1 D2 IN914 R8 22K
+
T
VR1 MOV V250L20
R R9 10K Q1 2N2222A +5
22K
FIGURE 1: Basic Box Modem with Dual-Supply Hybrid
25
73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem
DIRECT ACCESS ARRANGEMENT (DAA) The telephone line interfaces show two examples of how the "hybrid" may be implemented. The split supply design (Figure 1) is a typical two op-amp hybrid. The receive op-amp serves two purposes. It supplies gain to amplify the receive signal to the proper level for the modem's detectors and demodulator, and it removes the transmitted signal from the receive signal present at the transformer. This is done by supplying a portion of the transmitted signal to the non-inverting input of the receive op-amp at the same amplitude as the signal appearing at the transformer, making the transmit signal common mode. The single-supply hybrid is more complex than the dual-supply version described above, but its use eliminates the need for a second power supply. This circuit (Figure 2) uses a bridged drive to allow undistorted signals to be sent with a single 5 volt supply. Because DTMF tones utilize a higher amplitude than data, these signals will clip if a singleended drive approach is used. The bridged driver uses an extra op-amp (U1A) to invert the signal coming from the gain setting op-amp (U1B)
C1 390 pF
before sending it to the other leg of the transformer. Each op-amp then supplies half the drive signal to the transformer. The receive amplifier (U1C) picks off its signal at the junction of the impedance matching resistor and the transformer. Because the bottom leg of the transformer is being driven in one direction by U1A and the resistor is driven in the opposite direction at the same time by U1B, the junction of the transformer and resistor remains relatively constant and the receive signal is unaffected. DESIGN CONSIDERATIONS TDK Semiconductor's 1-chip modem products include all basic modem functions. This makes these devices adaptable for use in a variety of applications, and as easy to control as conventional digital bus peripherals. Unlike digital logic circuitry, modem designs must properly contend with precise frequency tolerances and very low level analog signals, to ensure acceptable performance. Using good analog circuit design practices will generally result in a sound design. Following are additional recommendations which should be taken into consideration when starting new designs.
R4 37.4K 1% C3 0.1 F RXA C4 0.0047 F R1 20K 1%
8
* U1C
+
9 10
R5 3.3K
R2 20K 1%
+5V 5 6
+ -
4 7 11* U1B
R3 475 1% T1 MIDCOM 671-8005 C10 0.47 F 250V C2 0.033 F
Note: Op-amp U1 must be rated for single 5V operation. R10 & R11 values depend on Op-amp used.
T +5V
R6 22.1K C6 0.1 F TXA R9 20K 1% D1 IN4004 R7 20K 1% C5 750 pF
U2 4N35
R13 22K
D2 3.3V ZENERS D3 1 +5V K1
VR1 MOV V250L20
R8 20K 1% 2 3 +5V VOLTAGE REFERENCE
R12 22K
+
* U1A
R10*
D4 IN914 R R14 10K Q1 2N2222A
R11*
C7 0.1 F
+
C8 10 F
HOOK RING
FIGURE 2: Single 5V Hybrid Version
26
73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem
CRYSTAL OSCILLATOR The K-Series crystal oscillator requires a parallel mode (antiresonant) crystal which operates at 11.0592 MHz. It is important that this frequency be maintained to within 0.01% accuracy. In order for a parallel mode crystal to operate correctly and to specification, it must have a load capacitor connected to the junction of each of the crystal and internal inverter connections, terminated to ground. The values of these capacitors depend primarily on the crystal's characteristics, and to a lesser degree on the internal inverter circuit. The values used affect the accuracy and start up characteristics of the oscillator. LAYOUT CONSIDERATIONS Good analog/digital design rules must be used to control system noise in order to obtain highest performance in modem designs. The more digital circuitry present on the PC board, the more this attention to noise control is needed. The modem should be treated as a high impedance analog device. A 22 F electrolytic capacitor in parallel with a 0.22 F ceramic capacitor between VDD and GND is recommended. Liberal use of ground planes and larger traces on power and ground are also highly favored. The ISET resistor and capacitor should be mounted near the ISET pin, away from digital signals. High speed digital circuits tend to generate a significant amount of EMI (Electro-Magnetic Interference) which must be minimized in order to meet regulatory agency limitations. To accomplish this, high speed digital devices should be locally bypassed, and the telephone line interface and K-Series device should be located close to each other near the area of the board where the phone line connection is accessed. To avoid problems, power supply and ground traces should be routed separately to the analog and digital functions on the board, and digital signals should not be routed near low level or high impedance analog traces. The analog and digital grounds should only connect at one point near the KSeries device ground pin to avoid ground loops. The K-Series modem IC's should have both high frequency and low frequency bypassing as close to the package as possible. MODEM PERFORMANCE CHARACTERISTICS The curves presented here define modem IC performance under a variety of line conditions while inducing disturbances that are typical of those encountered during data transmission on public service telephone lines. Test data was taken using an AEA Electronics' "Autotest I" modem test set and line simulator, operating under computer control. All tests were run fullduplex, using a Hayes SmartModemTM 2400 as the reference modem. A 511 pseudo-random-bit pattern was used for each data point. Noise was C-message weighted and all signal-to-noise (S/N) ratios reflect total power measurements similar to the CCITT V.56 measurement specification. The individual tests are defined as follows. BER vs. S/N This test measures the ability of the modem to operate over noisy lines with a minimum of datatransfer errors. Since some noise is generated in the best of dial-up lines, the modem must operate with the lowest S/N ratio possible. Better modem performance is indicated by test curves that are closest to the BER axis. A narrow spread between curves representing the four line parameters indicates minimal variation in performance while operating over a range of aberrant operating conditions. Typically, a modem will exhibit better BER-performance test curves receiving in the low band than in the high band. BER vs. Receive Level This test measures the dynamic range of the modem. Because signal levels vary widely over dial-up lines, the widest possible dynamic range is desirable. The minimum Bell specification calls for 36 dB of dynamic range. S/N ratios are held constant at the indicated values while the receive level is lowered from a very high to very low signal levels. The width of the "bowl" of these curves, taken at the BER point, is the measure of dynamic range.
27
73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem
28
73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem
29
73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem
MECHANICAL SPECIFICATIONS 28-Pin DIP
28-Pin PLCC
30
73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem
MECHANICAL SPECIFICATIONS (continued) 44-Lead TQFP
31
73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem
PACKAGE PIN DESIGNATIONS (Top View)
CLK XTL1 XTL2 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 ALE WR RD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
CAUTION: Use handling procedures necessary for a static sensitive component.
GND RXA VREF RESET ISET RXCLK RXD TXD CS EXCLK TXCLK INT TXA VDD
4 5 6 7 8 9 10 11
3
2
1
28 27 26 25 24
PLCC PINOUTS ARE THE SAME AS THE 28-PIN DIP
23 22 21 20 19
12 13 14 15 16 17 18
600-Mil 28-Pin DIP 73K224L-IP
28-Pin PLCC 73K224L-28IH
44-Lead TQFP 73K224L-IGT
ORDERING INFORMATION PART DESCRIPTION
73K224L with Parallel Bus Interface 28-Pin Plastic Dual In-Line 28-Pin Plastic Leaded Chip Carrier 44-Pin Thin Quad Flat Pack 73K224L-IP 73K224L-IH 73K224L-IGT 73K224L-IP 73K224L-IH 73K224L-IGT
ORDER NO.
PACKAGE MARK
No responsibility is assumed by TDK Semiconductor Corporation for use of this product nor for any infringements of patents and trademarks or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of TDK Semiconductor Corporation, and the company reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet is current before placing orders. TDK Semiconductor Corporation, 2642 Michelle Drive, Tustin, CA 92780-7019, (714) 508-8800, FAX: (714) 508-8877 Protected by the following Patents (4,777,453) (4,789,995) (4,847,868) (4,866,739) (c) 1996 TDK Semiconductor Corporation 04/24/00 - rev. E
32

▲Up To Search▲

Price & Availability of 73K224L-IGT

	To Download 73K224L-IGT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .